linux-kernel - [PATCH v6 0/3] ARM: dts: imx7: add NAND support

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Message-Id: <cover.9fab78eaa869dbad4c9ad7e8578c9cef3e49daa8.1496961128.git-series.stefan@agner.ch>
Date:   Thu,  8 Jun 2017 15:34:46 -0700
From:   Stefan Agner <stefan@...er.ch>
To:     shawnguo@...nel.org, kernel@...gutronix.de, sboyd@...eaurora.org
Cc:     aisheng.dong@....com, dwmw2@...radead.org,
        computersforpeace@...il.com, boris.brezillon@...e-electrons.com,
        marek.vasut@...il.com, richard@....at, robh+dt@...nel.org,
        mark.rutland@....com, han.xu@....com, fabio.estevam@...escale.com,
        LW@...O-electronics.de, linux-mtd@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Stefan Agner <stefan@...er.ch>
Subject: [PATCH v6 0/3] ARM: dts: imx7: add NAND support

This revision alters the clock tree such that the clock required by
the APBH DMA (NAND_USDHC_BUS_CLK_ROOT _after_ gate CCGR20) is available
as an independent clock.

So far the gate CCGR20 was used by the NAND_ROOT_CLK only. A previous
patch added the NAND_ROOT_CLK to the APBH DMA which lead the clock
gate CCGR20 getting enabled:
https://patchwork.ozlabs.org/patch/551967/

The data sheet seems to indicate that the APBH DMA only uses hclk which
is connected to NAND_USDHC_BUS_CLK_ROOT, but also through gate CCGR20.
Tests seem to confirm this wiring.

By adding a new clock IMX7D_NAND_USDHC_BUS_RAWNAND_CLK we can assign
a clock which also enables the shared CCGR20 gate without changing the
DMA driver. This better reflects the true wiring and encapsulates the
SoC specific clock wiring in the clock tree instead leaking it into
the driver code.

The wording "rawnand" has been taken from Table 5-12, Module APBHDMA
in the i.MX 7 Reference Manual.

Versions 2 and earlier also included NAND driver changes, which are
already merged.

--
Stefan

Changes since v5:
- Remove clock-names from dma-apbh node

Changes since v4:
- Introduce *_RAWNAND_CLK which represent clocks after CCGR20
- Use *_RAWNAND_CLK for APBH DMA and GPMI NAND
- Use assigned-clocks to set a reasonable parent for NAND_ROOT_SRC

Changes since v3:
- Only specify IMX7D_NAND_USDHC_BUS_ROOT_CLK which seems to be sufficent

Changes since v2:
- Dropped driver changes, alreay merged

Changes since v1:
- Make clks_count const
- Introduce IS_IMX7D for i.MX 7 SoC's and make it part of GPMI_IS_MX6

Stefan Agner (3):
  clk: imx7d: create clocks behind rawnand clock gate
  ARM: dts: imx7: add GPMI NAND and APBH DMA
  ARM: dts: imx7-colibri: add NAND support

 arch/arm/boot/dts/imx7-colibri.dtsi     |  9 ++++++++-
 arch/arm/boot/dts/imx7s.dtsi            | 31 ++++++++++++++++++++++++++-
 drivers/clk/imx/clk-imx7d.c             |  6 +++--
 include/dt-bindings/clock/imx7d-clock.h |  4 ++-
 4 files changed, 47 insertions(+), 3 deletions(-)

base-commit: e2bb3be2c6c623ff0bad975dc9435531f450f0c5
-- 
git-series 0.9.1