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Message-ID: <CACRpkdZPm0OxQodqy8pxLaEGjX1SCY5bsbraKiHHMZTanrQfJw@mail.gmail.com>
Date: Fri, 9 Jun 2017 13:02:21 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/3] pinctrl: intel: Add support for variable size pad groups
On Tue, Jun 6, 2017 at 3:18 PM, Mika Westerberg
<mika.westerberg@...ux.intel.com> wrote:
> The Intel GPIO hardware has a concept of pad groups, which means 1 to 32
> pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The
> existing hardware has the same amount of pads in each pad group (except the
> last one) so it is possible to use community->gpp_size to calculate start
> offset of each register.
>
> With the next generation SoCs the pad group size is not always the same
> anymore which means we cannot use community->gpp_size for register offset
> calculations directly.
>
> To support variable size pad groups we introduce struct intel_padgroup that
> can be filled in by the client drivers according the hardware pad group
> layout. The core driver will always use these when it performs calculations
> for pad register offsets. The core driver will automatically populate pad
> groups based on community->gpp_size if the driver does not provide any.
> This makes sure the existing drivers still work as expected.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
> Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@...el.com>
> Signed-off-by: Tan Jui Nee <jui.nee.tan@...el.com>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@...il.com>
Patch applied!
Yours,
Linus Walleij
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