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Message-ID: <CAOMZO5B95Gh5ufc0TUpqEvC4jwTww+AkcMPfdMG-Cj3Vv4Necg@mail.gmail.com>
Date: Fri, 9 Jun 2017 09:18:35 -0300
From: Fabio Estevam <festevam@...il.com>
To: Leonard Crestez <leonard.crestez@....com>
Cc: Shawn Guo <shawnguo@...nel.org>, Bai Ping <ping.bai@....com>,
"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Eduardo Valentin <edubezval@...il.com>,
Sascha Hauer <kernel@...gutronix.de>,
Fabio Estevam <fabio.estevam@....com>,
Zhang Rui <rui.zhang@...el.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 2/2] ARM: dts: imx6ul: Add imx6ul-tempmon
On Fri, Jun 9, 2017 at 7:58 AM, Leonard Crestez <leonard.crestez@....com> wrote:
> Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock
> directly. This is similar to other imx6 SOCs. This PLL is used for
> stuff like USB but not only that. My understanding is the _USB_OTG
> suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non-
> usb components use PLL3 (like UART) but through other gates/dividers.
Yes, PLL3 can be a parent for the UART clock, but UART has its own clock gate.
> Setting this to IMX6UL_CLK_DUMMY will cause temperature reads to fail.
> Even if PLL3 usually ends up being constantly enabled because of uarts
> this is not true at imx_thermal_probe time (or uarts can be disabled).
Ok, thanks for confirming. It was not obvious from reading the
reference manual that the PLL3 clock is the gate for tempmon.
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