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Date: Wed, 14 Jun 2017 09:49:29 -0700 From: Dan Williams <dan.j.williams@...el.com> To: Jan Kara <jack@...e.cz> Cc: "linux-nvdimm@...ts.01.org" <linux-nvdimm@...ts.01.org>, dm-devel@...hat.com, Matthew Wilcox <mawilcox@...rosoft.com>, X86 ML <x86@...nel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Christoph Hellwig <hch@....de>, Jeff Moyer <jmoyer@...hat.com>, Ingo Molnar <mingo@...hat.com>, "Oliver O'Halloran" <oohall@...il.com>, Al Viro <viro@...iv.linux.org.uk>, "H. Peter Anvin" <hpa@...or.com>, linux-fsdevel <linux-fsdevel@...r.kernel.org>, Thomas Gleixner <tglx@...utronix.de>, Ross Zwisler <ross.zwisler@...ux.intel.com> Subject: Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to libnvdimm On Wed, Jun 14, 2017 at 3:54 AM, Jan Kara <jack@...e.cz> wrote: > On Fri 09-06-17 13:24:29, Dan Williams wrote: >> With all calls to this routine re-directed through the pmem driver, we can kill >> the pmem api indirection. arch_wb_cache_pmem() is now optionally supplied by >> the arch specific asm/pmem.h. Same as before, pmem flushing is only defined >> for x86_64, but it is straightforward to add other archs in the future. >> >> Cc: <x86@...nel.org> >> Cc: Jan Kara <jack@...e.cz> >> Cc: Jeff Moyer <jmoyer@...hat.com> >> Cc: Ingo Molnar <mingo@...hat.com> >> Cc: Christoph Hellwig <hch@....de> >> Cc: "H. Peter Anvin" <hpa@...or.com> >> Cc: Thomas Gleixner <tglx@...utronix.de> >> Cc: Oliver O'Halloran <oohall@...il.com> >> Cc: Matthew Wilcox <mawilcox@...rosoft.com> >> Cc: Ross Zwisler <ross.zwisler@...ux.intel.com> >> Signed-off-by: Dan Williams <dan.j.williams@...el.com> > > Looks good to me. Just one question below... > >> -/** >> - * arch_wb_cache_pmem - write back a cache range with CLWB >> - * @vaddr: virtual start address >> - * @size: number of bytes to write back >> - * >> - * Write back a cache range using the CLWB (cache line write back) >> - * instruction. Note that @size is internally rounded up to be cache >> - * line size aligned. >> - */ >> static inline void arch_wb_cache_pmem(void *addr, size_t size) >> { >> - u16 x86_clflush_size = boot_cpu_data.x86_clflush_size; >> - unsigned long clflush_mask = x86_clflush_size - 1; >> - void *vend = addr + size; >> - void *p; >> - >> - for (p = (void *)((unsigned long)addr & ~clflush_mask); >> - p < vend; p += x86_clflush_size) >> - clwb(p); >> + clean_cache_range(addr,size); >> } > > So this will make compilation break on 32-bit x86 as it does not define > clean_cache_range(). Do we somewhere force we are on x86_64 when pmem is > enabled? Yes, this is enforced by: select ARCH_HAS_PMEM_API if X86_64 ...in arch/x86/Kconfig. We fallback to a dummy arch_wb_cache_pmem() implementation and emit this warning for !ARCH_HAS_PMEM_API archs: "nd_pmem namespace0.0: unable to guarantee persistence of writes"
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