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Message-ID: <3a617630-2406-da49-707c-4959a2afd8e1@intel.com>
Date: Wed, 14 Jun 2017 14:58:30 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Jerome Glisse <jglisse@...hat.com>
Cc: linux-kernel@...r.kernel.org, linux-mm@...ck.org,
John Hubbard <jhubbard@...dia.com>,
David Nellans <dnellans@...dia.com>, cgroups@...r.kernel.org,
Dan Williams <dan.j.williams@...el.com>,
Ross Zwisler <ross.zwisler@...ux.intel.com>,
Johannes Weiner <hannes@...xchg.org>,
Michal Hocko <mhocko@...nel.org>,
Vladimir Davydov <vdavydov.dev@...il.com>,
Balbir Singh <balbirs@....ibm.com>,
Aneesh Kumar <aneesh.kumar@...ux.vnet.ibm.com>,
"Paul E . McKenney" <paulmck@...ux.vnet.ibm.com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>
Subject: Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM
On 06/14/2017 02:38 PM, Jerome Glisse wrote:
> On Wed, Jun 14, 2017 at 02:20:23PM -0700, Dave Hansen wrote:
>> On 06/14/2017 01:11 PM, Jérôme Glisse wrote:
>>> Cache coherent device memory apply to architecture with system bus
>>> like CAPI or CCIX. Device connected to such system bus can expose
>>> their memory to the system and allow cache coherent access to it
>>> from the CPU.
>> How does this interact with device memory that's enumerated in the new
>> ACPI 6.2 HMAT? That stuff is also in the normal e820 and, by default,
>> treated as normal system RAM. Would this mechanism be used for those
>> devices as well?
>>
>> http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf
> It doesn't interact with that. HMM-CDM is a set of helper that don't
> do anything unless instructed so. So for device memory to be presented
> as HMM-CDM you need to hotplug it as ZONE_DEVICE(DEVICE_PUBLIC) which
> can be done with the helper introduced in patch 2 of this patchset.
I guess I'm asking whether we *should* instruct HMM-CDM to manage all
coherent device memory. If not, where do we draw the line for what we
use HMM-CDM, and for what we use the core MM?
> I don't think that the HMAT inside ACPI is restricted or even intended
> for device memory.
It can definitely describe memory attached to memory controllers which
are not directly attached to CPUs. That means either some kind of
memory expander, or device memory.
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