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Message-ID: <CACRpkdb6i+O1okCb2tbSECdzjzsyBsff-q-2UQ16gX7yW+Xu8Q@mail.gmail.com>
Date: Fri, 16 Jun 2017 11:24:33 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Gregory CLEMENT <gregory.clement@...e-electrons.com>
Cc: "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Jason Cooper <jason@...edaemon.net>,
Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Rob Herring <robh+dt@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
Russell King <rmk+kernel@...linux.org.uk>,
Nadav Haklai <nadavh@...vell.com>,
Kostya Porotchkin <kostap@...vell.com>,
Neta Zur Hershkovits <neta@...vell.com>,
Marcin Wojtas <mw@...ihalf.com>,
Omri Itach <omrii@...vell.com>,
Shadi Ammouri <shadi@...vell.com>,
Hanna Hawa <hannah@...vell.com>,
Grzegorz Jaszczyk <jaz@...ihalf.com>
Subject: Re: [PATCH v3 6/9] pinctrl: mvebu: add driver for Armada CP110 pinctrl
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
<gregory.clement@...e-electrons.com> wrote:
> From: Hanna Hawa <hannah@...vell.com>
>
> This commit adds a pinctrl driver for the CP110 part of the Marvell
> Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
> the MPP pins are available. On the other side, the Armada 8K has two
> CP110, and the available MPPs are split between the master CP110 (MPPs 32
> to 62) and the slave CP110 (MPPs 0 to 31).
>
> The register interface to control the MPPs is however the same as all
> other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.
>
> Signed-off-by: Hanna Hawa <hannah@...vell.com>
> Reviewed-by: Shadi Ammouri <shadi@...vell.com>
Patch applied.
Yours,
Linus Walleij
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