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Message-Id: <20170616141322.30466-1-guodong.xu@linaro.org>
Date: Fri, 16 Jun 2017 22:13:22 +0800
From: Guodong Xu <guodong.xu@...aro.org>
To: robh+dt@...nel.org, mark.rutland@....com, lee.jones@...aro.org,
ulf.hansson@...aro.org, bhelgaas@...gle.com, xuwei5@...ilicon.com,
catalin.marinas@....com, will.deacon@....com,
wangkefeng.wang@...wei.com, arnd@...db.de,
xuejiancheng@...ilicon.com, puck.chen@...ilicon.com
Cc: zhangfei.gao@...aro.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mmc@...r.kernel.org, linux-pci@...r.kernel.org,
Xiaowei Song <songxiaowei@...ilicon.com>,
Guodong Xu <guodong.xu@...aro.org>
Subject: [PATCH v5 15/20] arm64: dts: hisi: add kirin pcie node
From: Xiaowei Song <songxiaowei@...ilicon.com>
Add PCIe node for hi3660
Cc: Guodong Xu <guodong.xu@...aro.org>
Signed-off-by: Xiaowei Song <songxiaowei@...ilicon.com>
Acked-by: Arnd Bergmann <arnd@...db.de>
Changes in v5:
* fix interrupt-map, to conform to gic's #address-cells = <0>
* remove redundant status = "ok"
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index e138973..8183d71 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -754,5 +754,41 @@
cs-gpios = <&gpio18 5 0>;
status = "disabled";
};
+
+ pcie@...00000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys",
+ "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
};
};
--
2.10.2
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