linux-kernel - Re: [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

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Message-ID: <20170620000312.GS20170@codeaurora.org>
Date:   Mon, 19 Jun 2017 17:03:12 -0700
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Dinh Nguyen <dinguyen@...nel.org>
Cc:     linux-clk@...r.kernel.org, mturquette@...libre.com,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

On 06/08, Dinh Nguyen wrote:
> The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
> offset by 1 additional bit.
> 
> Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
> Stratix10 platforms.
> 
> Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
> Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
> ---

Applied to clk-next

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