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Message-ID: <20170620010125.GI20170@codeaurora.org>
Date:   Mon, 19 Jun 2017 18:01:25 -0700
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Stefan Agner <stefan@...er.ch>
Cc:     shawnguo@...nel.org, kernel@...gutronix.de, aisheng.dong@....com,
        dwmw2@...radead.org, computersforpeace@...il.com,
        boris.brezillon@...e-electrons.com, marek.vasut@...il.com,
        richard@....at, robh+dt@...nel.org, mark.rutland@....com,
        han.xu@....com, fabio.estevam@...escale.com,
        LW@...O-electronics.de, linux-mtd@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 1/3] clk: imx7d: create clocks behind rawnand clock
 gate

On 06/08, Stefan Agner wrote:
> The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
> and NAND_CLK_ROOT. However, the gate has been in the chain of the
> latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
> only, e.g. as required by APBH-Bridge-DMA.
> 
> Add new clocks which represent the clock after the gate, and use a
> shared clock gate to correctly model the hardware.
> 
> Signed-off-by: Stefan Agner <stefan@...er.ch>
> Tested-by: Fabio Estevam <fabio.estevam@....com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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