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Date: Wed, 21 Jun 2017 19:43:20 +0200 From: Borislav Petkov <bp@...en8.de> To: Andy Lutomirski <luto@...nel.org> Cc: x86@...nel.org, linux-kernel@...r.kernel.org, Linus Torvalds <torvalds@...ux-foundation.org>, Andrew Morton <akpm@...ux-foundation.org>, Mel Gorman <mgorman@...e.de>, "linux-mm@...ck.org" <linux-mm@...ck.org>, Nadav Amit <nadav.amit@...il.com>, Rik van Riel <riel@...hat.com>, Dave Hansen <dave.hansen@...el.com>, Arjan van de Ven <arjan@...ux.intel.com>, Peter Zijlstra <peterz@...radead.org> Subject: Re: [PATCH v3 04/11] x86/mm: Give each mm TLB flush generation a unique ID On Tue, Jun 20, 2017 at 10:22:10PM -0700, Andy Lutomirski wrote: > - * The x86 doesn't have a mmu context, but > - * we put the segment information here. > + * x86 has arch-specific MMU state beyond what lives in mm_struct. > */ > typedef struct { > + /* > + * ctx_id uniquely identifies this mm_struct. A ctx_id will never > + * be reused, and zero is not a valid ctx_id. > + */ > + u64 ctx_id; > + > + /* > + * Any code that needs to do any sort of TLB flushing for this > + * mm will first make its changes to the page tables, then > + * increment tlb_gen, then flush. This lets the low-level > + * flushing code keep track of what needs flushing. > + * > + * This is not used on Xen PV. > + */ > + atomic64_t tlb_gen; Btw, can this just be a 4-byte int instead? I.e., simply atomic_t. I mean, it should be enough for all the TLB generations in flight, no? -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
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