linux-kernel - [tip:irq/core] x86/apic: Mark single target interrupts

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Message-ID: <tip-3ca57222c36ba31b80aa25de313f3c8ab26a8102@git.kernel.org>
Date:   Thu, 22 Jun 2017 10:10:14 -0700
From:   tip-bot for Thomas Gleixner <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     hch@....de, tglx@...utronix.de, mingo@...nel.org,
        mpe@...erman.id.au, linux-kernel@...r.kernel.org,
        keith.busch@...el.com, peterz@...radead.org, axboe@...nel.dk,
        hpa@...or.com, marc.zyngier@....com
Subject: [tip:irq/core] x86/apic: Mark single target interrupts

Commit-ID:  3ca57222c36ba31b80aa25de313f3c8ab26a8102
Gitweb:     http://git.kernel.org/tip/3ca57222c36ba31b80aa25de313f3c8ab26a8102
Author:     Thomas Gleixner <tglx@...utronix.de>
AuthorDate: Tue, 20 Jun 2017 01:37:54 +0200
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Thu, 22 Jun 2017 18:21:26 +0200

x86/apic: Mark single target interrupts

If the interrupt destination mode of the APIC is physical then the
effective affinity is restricted to a single CPU.

Mark the interrupt accordingly in the domain allocation code, so the core
code can avoid pointless affinity setting attempts.

Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Jens Axboe <axboe@...nel.dk>
Cc: Marc Zyngier <marc.zyngier@....com>
Cc: Michael Ellerman <mpe@...erman.id.au>
Cc: Keith Busch <keith.busch@...el.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Christoph Hellwig <hch@....de>
Link: http://lkml.kernel.org/r/20170619235447.508846202@linutronix.de

---
 arch/x86/kernel/apic/vector.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
index b270a76..2567dc0 100644
--- a/arch/x86/kernel/apic/vector.c
+++ b/arch/x86/kernel/apic/vector.c
@@ -371,6 +371,13 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
 					       irq_data);
 		if (err)
 			goto error;
+		/*
+		 * If the apic destination mode is physical, then the
+		 * effective affinity is restricted to a single target
+		 * CPU. Mark the interrupt accordingly.
+		 */
+		if (!apic->irq_dest_mode)
+			irqd_set_single_target(irq_data);
 	}
 
 	return 0;