linux-kernel - Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0

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Message-ID: <20170628185538.ibwyv5pxpzf7liuu@pd.tnic>
Date:   Wed, 28 Jun 2017 20:55:38 +0200
From:   Borislav Petkov <bp@...e.de>
To:     "Ghannam, Yazen" <Yazen.Ghannam@....com>
Cc:     Jack Miller <jack@...ezen.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 !=
 thread 0

On Wed, Jun 28, 2017 at 06:51:08PM +0000, Ghannam, Yazen wrote:
> The non-core MCA banks are only visible to a "master thread" on each Die. The
> master thread is the first one on the Die. Since we have the same banks on each
> Die we only need to read them once, and I assumed that CPU0 would always be
> there.

Right, I believe this is similar to the node-base core thing. Or
something to that effect.

So is there a reliable way to find out which is the node-base core, or
the master thread? Because regardless what fw does, it should still
configure such master thread if the BSP is a different thread.

So if our code would be able to find that out, we should be good.

 [ Practically, a sane fw would simply go and make the new BSP also the master
   thread. But "sane" and "fw" in a sentence don't work. :-) ]

Thanks.

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--