lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAK8P3a3Pg2rm8nSPUm_E61F7+zSr3gWV6sNqhC0Et3Zh2xPtmA@mail.gmail.com>
Date:   Thu, 29 Jun 2017 17:07:35 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Andreas Färber <afaerber@...e.de>
Cc:     Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        mp-cs@...ions-semi.com, Thomas Liau <thomas.liau@...ions-semi.com>,
        张东风 <zhangdf@...ions-semi.com>,
        刘炜 <liuwei@...ions-semi.com>,
        张天益 <tyzhang@...ions-semi.com>,
        96boards@...obotics.com, support@...aker.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Russell King <linux@...linux.org.uk>
Subject: Re: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500

>> +static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
>> +{
>> +       unsigned long timeout;
>> +       int ret;
>> +
>> +       ret = s500_wakeup_secondary(cpu);
>> +       if (ret)
>> +               return ret;
>> +
>> +       udelay(10);
>> +
>> +       spin_lock(&boot_lock);
>> +
>> +       /*
>> +        * The secondary processor is waiting to be released from
>> +        * the holding pen - release it, then wait for it to flag
>> +        * that it has been released by resetting pen_release.
>> +        */
>> +       write_pen_release(cpu_logical_map(cpu));
>> +       smp_send_reschedule(cpu);
>> +
>> +       timeout = jiffies + (1 * HZ);
>> +       while (time_before(jiffies, timeout)) {
>> +               if (pen_release == -1)
>> +                       break;
>> +       }
>> +
>> +       writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
>> +       writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
>> +
>> +       spin_unlock(&boot_lock);
>> +
>> +       return pen_release != -1 ? -ENOSYS : 0;
>> +}
>
> This looks more complicated than necessary. Why do you need the holding
> pen when you have a register to start up the CPU?
>

It seems you missed my question here. Can you please follow up, and
if possible send a patch to remove the pen_release logic that appears
to be unnecessary here?

        Arnd

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ