linux-kernel - Re: [PATCH 2/3] dts: RISC-V local interrupt controller docs

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Message-ID: <20170629203028.qv6r4kj6fyu3hxfz@rob-hp-laptop>
Date:   Thu, 29 Jun 2017 15:30:28 -0500
From:   Rob Herring <robh@...nel.org>
To:     Palmer Dabbelt <palmer@...belt.com>
Cc:     tglx@...utronix.de, jason@...edaemon.net, marc.zyngier@....com,
        mark.rutland@....com, jic23@...nel.org, treding@...dia.com,
        maxime.ripard@...e-electrons.com, marek.vasut@...il.com,
        ccc94453@....cybercity.dk, gregkh@...uxfoundation.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 2/3] dts: RISC-V local interrupt controller docs

On Mon, Jun 26, 2017 at 10:21:23PM -0700, Palmer Dabbelt wrote:
> This patch adds documentation on the RISC-V local interrupt controller,
> which is a per-hart interrupt controller that manages all interrupts
> entering a RISC-V hart.  This interrupt controller is present on all
> RISC-V systems.

"dt-bindings: interrupt-controller: ..." for the subject. Similar for 
the other patches.

> 
> Signed-off-by: Palmer Dabbelt <palmer@...belt.com>
> ---
>  .../interrupt-controller/riscv,cpu-intc.txt        | 70 ++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
> new file mode 100644
> index 000000000000..f4906f49a1b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
> @@ -0,0 +1,70 @@
> +RISC-V Hart-Level Interrupt Controller (HLIC)
> +---------------------------------------------
> +
> +RISC-V cores include Control Status Registers (CSRs) which are local to each
> +hart and can be read or written by software. Some of these CSRs are used to

What's a hart? Please define.

> +control local interrupts connected to the core.  Every interrupt is ultimately
> +routed through a hart's HLIC before it interrupts that hart.
> +
> +The RISC-V supervisor ISA manual specifices three interrupt sources that are
> +attached to every HLIC: software interrupts, the timer interrupt, and external
> +interrupts.  Software interrupts are used to send IPIs between cores.  The
> +timer interrupt comes from an architectually mandated real-time timer that is
> +controller via SBI calls and CSR reads.  External interrupts connect all other
> +device interrupts to the HLIC, which are routed via the platforw-level

s/platforw/platform/

> +interrupt contrellor (PLIC).

another typo

> +
> +All RISC-V systems that conform to the supervisor ISA specification are
> +required to have a HLIC with these three interrupt sources present.
> +
> +Required properties:
> +- compatible : "riscv,cpu-intc"

Only one version? 

> +- #interrupt-cells : should be <1>
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +Furthermore, this interrupt-controller MUST be embedded inside the cpu
> +definition of the hart whose CSRs control these local interrupts.
> +
> +An example of a device tree entry for a standard RISC-V hart is as follows:
> +
> +	cpu1: cpu@1 {
> +		clock-frequency = <1600000000>;
> +		compatible = "riscv";

This is not really specific enough. You need cpu node documentation 
for this as well.

> +		d-cache-block-size = <64>;
> +		d-cache-sets = <64>;
> +		d-cache-size = <16384>;
> +		d-tlb-sets = <1>;
> +		d-tlb-size = <32>;
> +		device_type = "cpu";
> +		i-cache-block-size = <64>;
> +		i-cache-sets = <64>;
> +		i-cache-size = <16384>;
> +		i-tlb-sets = <1>;
> +		i-tlb-size = <32>;
> +		mmu-type = "riscv,sv39";

This and ...

> +		next-level-cache = <&L2>;
> +		reg = <1>;
> +		riscv,isa = "rv64imac";

... this should be implied by specific compatible strings.

> +		status = "okay";
> +		tlb-split;
> +		cpu1-intc: interrupt-controller {
> +			#interrupt-cells = <1>;
> +			compatible = "riscv,cpu-intc";
> +			interrupt-controller;
> +		};
> +	};
> +
> +The sections specifically relevant to the HLIC are
> +
> +	cpu1: cpu@1 {

Just remove the above and add this which is enough for the example:

		compatible = "riscv";
		...

> +		cpu1-intc: interrupt-controller {
> +			#interrupt-cells = <1>;
> +			compatible = "riscv,cpu-intc";
> +			interrupt-controller;
> +		};
> +	};
> +
> +As the HLIC is essentially a static interrupt controller, this device tree
> +entry essentially just indicates the presence of a HLIC.  All HLIC interrupts

Won't it also show the connections to the timer, PLIC, etc.?

> +are level-triggered, so there is no need to specify this as part of the device
> +tree.
> -- 
> 2.13.0
>