lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170629221118.fwnwe7k7ykx2acr3@piout.net>
Date:   Fri, 30 Jun 2017 00:11:18 +0200
From:   Alexandre Belloni <alexandre.belloni@...e-electrons.com>
To:     Rob Herring <robh@...nel.org>
Cc:     Quentin Schulz <quentin.schulz@...e-electrons.com>,
        mturquette@...libre.com, sboyd@...eaurora.org,
        mark.rutland@....com, nicolas.ferre@...rochip.com,
        linux@...linux.org.uk, boris.brezillon@...e-electrons.com,
        lgirdwood@...il.com, broonie@...nel.org, perex@...ex.cz,
        tiwai@...e.com, Nicolas Ferre <nicolas.ferre@...el.com>,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        alsa-devel@...a-project.org, thomas.petazzoni@...e-electrons.com
Subject: Re: [PATCH 2/6] clk: at91: add audio pll clock driver

Hi,

On 29/06/2017 at 16:47:58 -0500, Rob Herring wrote:
> On Fri, Jun 23, 2017 at 11:00:55AM +0200, Quentin Schulz wrote:
> > From: Nicolas Ferre <nicolas.ferre@...el.com>
> > 
> > This new clock driver set allows to have a fractional divided clock that
> > would generate a precise clock particularly suitable for audio
> > applications.
> > 
> > The main audio pll clock has two children clocks: one that is connected
> > to the PMC, the other that can directly drive a pad. As these two routes
> > have different enable bits and different dividers and divider formula,
> > they are handled by two different drivers. Each of them could modify the
> > rate of the main audio pll parent.
> > The main audio pll clock can output 620MHz to 700MHz.
> > 
> > Signed-off-by: Nicolas Ferre <nicolas.ferre@...el.com>
> > Signed-off-by: Quentin Schulz <quentin.schulz@...e-electrons.com>
> > ---
> >  .../devicetree/bindings/clock/at91-clock.txt       |  10 +
> 
> It would be nice to see at91 to transition away from a node per clock to 
> just clock controller nodes. In any case:
> 

Yes, that is exactly our plan.

> Acked-by: Rob Herring <robh@...nel.org>
> 
> >  arch/arm/mach-at91/Kconfig                         |   4 +
> >  drivers/clk/at91/Makefile                          |   2 +
> >  drivers/clk/at91/clk-audio-pll-pad.c               | 204 ++++++++++++++++++
> >  drivers/clk/at91/clk-audio-pll-pmc.c               | 175 +++++++++++++++
> >  drivers/clk/at91/clk-audio-pll.c                   | 237 +++++++++++++++++++++
> >  include/linux/clk/at91_pmc.h                       |  25 +++
> >  sound/soc/atmel/atmel-classd.c                     |  20 +-
> >  8 files changed, 658 insertions(+), 19 deletions(-)
> >  create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c
> >  create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c
> >  create mode 100644 drivers/clk/at91/clk-audio-pll.c

-- 
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ