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Message-ID: <1498802721-32455-3-git-send-email-zhi.mao@mediatek.com>
Date: Fri, 30 Jun 2017 14:05:17 +0800
From: Zhi Mao <zhi.mao@...iatek.com>
To: <john@...ozen.org>, Thierry Reding <thierry.reding@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
<linux-pwm@...r.kernel.org>
CC: <srv_heupstream@...iatek.com>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, <zhi.mao@...iatek.com>,
<yingjoe.chen@...iatek.com>, <yt.shen@...iatek.com>,
<sean.wang@...iatek.com>, <zhenbao.liu@...iatek.com>
Subject: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
In original code, the pwm output frequency is not correct
when set bit<3>=1 to PWMCON register.
Signed-off-by: Zhi Mao <zhi.mao@...iatek.com>
---
drivers/pwm/pwm-mediatek.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5c11bc7..d08b5b3 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
if (clkdiv > 7)
return -EINVAL;
- mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
--
1.7.9.5
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