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Message-Id: <20170630112109.13785-3-enric.balletbo@collabora.com>
Date: Fri, 30 Jun 2017 13:21:08 +0200
From: Enric Balletbo i Serra <enric.balletbo@...labora.com>
To: Thierry Reding <thierry.reding@...il.com>,
Lee Jones <lee.jones@...aro.org>,
Daniel Thompson <daniel.thompson@...aro.org>,
Jingoo Han <jingoohan1@...il.com>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
Rob Herring <robh+dt@...nel.org>, Pavel Machek <pavel@....cz>,
Richard Purdie <rpurdie@...ys.net>,
Jacek Anaszewski <jacek.anaszewski@...il.com>,
Heiko Stuebner <heiko@...ech.de>
Cc: linux-pwm@...r.kernel.org, linux-fbdev@...r.kernel.org,
linux-kernel@...r.kernel.org, groeck@...omium.org,
linux-rockchip@...ts.infradead.org
Subject: [PATCH v2 3/4] ARM: dts: rockchip: set pre/post pwm-delay-us property.
For veyron the binding should provide both pwm timings, the delay between
you enable the PWM and set the enable signal, and the delay between you
disable the PWM signal and clear the enable signal. Update the binding
accordingly, in this case the panels connected to the veyron boards have
a symetric power sequence, hence the same value is used.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
---
Changes since v1:
- Add this new patch to fix current binding on veyron.
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index d752a31..c0e8ce2 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -96,7 +96,7 @@
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
- pwm-delay-us = <10000>;
+ pwm-delay-us = <10000 10000>;
};
gpio-charger {
--
2.9.3
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