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Message-ID: <alpine.DEB.2.20.1707022111140.2296@nanos>
Date:   Sun, 2 Jul 2017 21:15:00 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Dou Liyang <douly.fnst@...fujitsu.com>
cc:     x86@...nel.org, linux-kernel@...r.kernel.org,
        xen-devel@...ts.xenproject.org, mingo@...nel.org, hpa@...or.com,
        ebiederm@...ssion.com, bhe@...hat.com, boris.ostrovsky@...cle.com,
        peterz@...radead.org, izumi.taku@...fujitsu.com
Subject: Re: [PATCH v5 08/12] x86/ioapic: Refactor the delay logic in
 timer_irq_works()

On Fri, 30 Jun 2017, Dou Liyang wrote:
> +static void __init delay_with_tsc(void)
> +{
> +	unsigned long long start, now;
> +	unsigned long ticks = jiffies;

Please make that

       unsigned long end = jiffies + 4;

ticks really means: number of ticks. But that variable is doing something
different.

> +	start = rdtsc();
> +
> +	/*
> +	 * We don't know the TSC frequency yet, but waiting for
> +	 * 40000000000/HZ TSC cycles is safe:
> +	 * 4 GHz == 10 jiffies
> +	 * 1 GHz == 40 jiffies
> +	 */
> +	do {
> +		rep_nop();
> +		now = rdtsc();
> +	} while ((now - start) < 40000000000UL / HZ &&
> +		time_before_eq(jiffies, ticks + 4));
> +}
> +
> +static void __init delay_without_tsc(void)
> +{
> +	int band = 1;
> +	unsigned long ticks = jiffies;

Please sort variables in reverse fir tree order

	unsigned long end = jiffies + 4;
	int band = 1;

> +
> +	/*
> +	 * We don't know any frequency yet, but waiting for
> +	 * 40940000000/HZ cycles is safe:
> +	 * 4 GHz == 10 jiffies
> +	 * 1 GHz == 40 jiffies
> +	 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
> +	 */
> +	do {
> +		__delay(((1 << band++) * 10000000UL) / HZ);

  s/1/1U/

> +	} while (band < 12 && time_before_eq(jiffies, ticks + 4));
> +}

Thanks,

	tglx

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