lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170704211749.jqgfbgjqzm2bcppy@excalibur.cnev.de>
Date:   Tue, 4 Jul 2017 23:17:50 +0200
From:   Karsten Merker <merker@...ian.org>
To:     Palmer Dabbelt <palmer@...belt.com>,
        Thomas Gleixner <tglx@...utronix.de>
Cc:     patches@...ups.riscv.org, peterz@...radead.org, mingo@...hat.com,
        mcgrof@...nel.org, viro@...iv.linux.org.uk, sfr@...b.auug.org.au,
        nicolas.dichtel@...nd.com, rmk+kernel@...linux.org.uk,
        msalter@...hat.com, tklauser@...tanz.ch, will.deacon@....com,
        james.hogan@...tec.com, paul.gortmaker@...driver.com,
        linux@...ck-us.net, linux-kernel@...r.kernel.org,
        linux-arch@...r.kernel.org, albert@...ive.com
Subject: Re: [patches] Re: [PATCH 1/9] RISC-V: Init and Halt Code

On Tue, Jul 04, 2017 at 10:37:37PM +0200, Thomas Gleixner wrote:
> On Tue, 4 Jul 2017, Palmer Dabbelt wrote:

> > +unsigned long riscv_timebase;
> > +
> > +static int next_event(unsigned long delta, struct clock_event_device *ce)
> > +{
> > +	BUG_ON(ce != timer_riscv_device(smp_processor_id()));
> > +	sbi_set_timer(get_cycles64() + delta);
> > +	return 0;
> > +}
> > +
> > +static unsigned long long rdtime(struct clocksource *cs)
> > +{
> > +	BUG_ON(cs != timer_riscv_source(smp_processor_id()));
> > +	return get_cycles64();
> > +}
> > +
> > +void riscv_timer_interrupt(void)
> > +{
> > +	int cpu = smp_processor_id();
> > +	struct clock_event_device *evdev = timer_riscv_device(cpu);
> > +
> > +	evdev->event_handler(evdev);
> > +}
> > +
> > +void __init time_init(void)
> > +{
> > +	struct device_node *cpu;
> > +	u32 prop;
> > +	int cpu_id = smp_processor_id();
> > +
> > +	cpu = of_find_node_by_path("/cpus");
> > +	if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
> > +		panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
> > +	riscv_timebase = prop;
> > +
> > +	lpj_fine = riscv_timebase / HZ;
> > +
> > +	timer_riscv_init(cpu_id, riscv_timebase, &rdtime, &next_event);
> 
> This function is nowhere.... Neither can I find the header file.

It is part of the RISC-V clock driver patchset, please cf.
https://github.com/riscv/riscv-linux/commit/0705a31372d4714e54c5104e02021441785c1fd5

https://github.com/riscv/riscv-linux/commits/riscv-for-submission-v4
has the various RISC-V-related driver patchsets merged in (in
addition to this arch patchset).

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ