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Message-ID: <mhng-a56cb230-6333-4bac-a093-546ad5dac8eb@palmer-si-x1c4>
Date: Mon, 10 Jul 2017 13:39:50 -0700 (PDT)
From: Palmer Dabbelt <palmer@...belt.com>
To: j.neuschaefer@....net
CC: patches@...ups.riscv.org, peterz@...radead.org, mingo@...hat.com,
mcgrof@...nel.org, viro@...iv.linux.org.uk, sfr@...b.auug.org.au,
nicolas.dichtel@...nd.com, rmk+kernel@...linux.org.uk,
msalter@...hat.com, tklauser@...tanz.ch, will.deacon@....com,
james.hogan@...tec.com, paul.gortmaker@...driver.com,
linux@...ck-us.net, linux-kernel@...r.kernel.org,
linux-arch@...r.kernel.org, albert@...ive.com
Subject: Re: [patches] [PATCH 2/9] RISC-V: Atomic and Locking Code
On Fri, 07 Jul 2017 06:16:07 PDT (-0700), j.neuschaefer@....net wrote:
> On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote:
> [...]
>> +/* These barries need to enforce ordering on both devices or memory. */
>
> Very minor nit: s/barries/barriers/ (in several places)
I think this should do it
https://github.com/riscv/riscv-linux/commit/b356e7a2223b5e21df424ea7e9900e5bf408762f
Thanks!
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