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Message-ID: <20170711090240.az5rabtlzpupbrq5@hirez.programming.kicks-ass.net>
Date: Tue, 11 Jul 2017 11:02:40 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Andi Kleen <ak@...ux.intel.com>
Cc: Aubrey Li <aubrey.li@...el.com>, tglx@...utronix.de,
len.brown@...el.com, rjw@...ysocki.net, tim.c.chen@...ux.intel.com,
arjan@...ux.intel.com, paulmck@...ux.vnet.ibm.com,
yang.zhang.wz@...il.com, x86@...nel.org,
linux-kernel@...r.kernel.org, Aubrey Li <aubrey.li@...ux.intel.com>
Subject: Re: [RFC PATCH v1 00/11] Create fast idle path for short idle periods
On Mon, Jul 10, 2017 at 10:27:05AM -0700, Andi Kleen wrote:
> On Mon, Jul 10, 2017 at 06:42:06PM +0200, Peter Zijlstra wrote:
> > I have, and last time I did the actual poking at the LAPIC (to make NOHZ
> > happen) was by far the slowest thing happening.
>
> That must have been a long time ago because modern systems use TSC deadline
> for a very long time ...
Its been a while, but I didn't use the very latest chip when I did.
> It's still slow, but not as slow as the LAPIC.
Deadline TSC is a LAPIC timer mode. Sure the MSR might be slightly
cheaper than the MMIO, but its still painful.
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