linux-kernel - RISC-V Linux Port v5

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Date:   Mon, 10 Jul 2017 18:39:07 -0700
From:   Palmer Dabbelt <palmer@...belt.com>
To:     yamada.masahiro@...ionext.com, mmarek@...e.com,
        will.deacon@....com, peterz@...radead.org, boqun.feng@...il.com,
        mingo@...hat.com, daniel.lezcano@...aro.org, tglx@...utronix.de,
        jason@...edaemon.net, marc.zyngier@....com,
        gregkh@...uxfoundation.org, jslaby@...e.com, davem@...emloft.net,
        mchehab@...nel.org, sfr@...b.auug.org.au, fweisbec@...il.com,
        viro@...iv.linux.org.uk, mcgrof@...nel.org, dledford@...hat.com,
        bart.vanassche@...disk.com, sstabellini@...nel.org,
        daniel.vetter@...ll.ch, mpe@...erman.id.au, msalter@...hat.com,
        nicolas.dichtel@...nd.com, james.hogan@...tec.com,
        paul.gortmaker@...driver.com, linux@...ck-us.net,
        heiko.carstens@...ibm.com, schwidefsky@...ibm.com,
        linux-kernel@...r.kernel.org, patches@...ups.riscv.org,
        akpm@...ux-foundation.org
Cc:     albert@...ive.com
Subject: RISC-V Linux Port v5

Thanks to everyone who has participated in the review process so far.  I've
based this patch set on the current master.  Things have really started to
calmn down, so this is fairly similar to the v4 patch set.  The most
interesting changes include:

 * We've moved back to a single patch set.

 * SMP support has been fixed, I was accidentally running on a non-SMP
   configuration.  There were various mistakes all over the tree as a result of
   this.

 * The cmpxchg syscalls have been removed, as they were deemed a bad idea.  As
   a result, RISC-V Linux systems mandate the A extension.  The cooresponding
   Kconfig entry to enable builds on non-A systems has been removed.

 * A few more atomic fixes: mostly fence changes, but those resulted in a
   handful of additional macros that were no longer necessary.

 * riscv_early_sie has been removed.

Like last time, in case one gets eaten by the mailing list this is also
available as a git tree on our Git Hub

  https://github.com/riscv/riscv-linux/tree/riscv-for-submission-arch-v5

Thanks to everyone who has helped review our port!

[PATCH 01/17] lib: Add shared copies of some GCC library routines
[PATCH 02/17] pci: Add a generic, weakly-linked
[PATCH 03/17] pci: Add a generic, weakly-linked pcibios_fixup_bus
[PATCH 04/17] MAINTAINERS: Add RISC-V
[PATCH 05/17] clocksource: New RISC-V SBI timer driver
[PATCH 06/17] irqchip: RISC-V Local Interrupt Controller Driver
[PATCH 07/17] irqchip: New RISC-V PLIC Driver
[PATCH 08/17] tty: New RISC-V SBI console driver
[PATCH 09/17] RISC-V: Init and Halt Code
[PATCH 10/17] RISC-V: Atomic and Locking Code
[PATCH 11/17] RISC-V: Generic library routines and assembly
[PATCH 12/17] RISC-V: ELF and module implementation
[PATCH 13/17] RISC-V: Task implementation
[PATCH 14/17] RISC-V: Device, timer, IRQs, and the SBI
[PATCH 15/17] RISC-V: Paging and MMU
[PATCH 16/17] RISC-V: User-facing API
[PATCH 17/17] RISC-V: Build Infastructure