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Message-Id: <20170711013924.22085-6-palmer@dabbelt.com>
Date: Mon, 10 Jul 2017 18:39:12 -0700
From: Palmer Dabbelt <palmer@...belt.com>
To: yamada.masahiro@...ionext.com, mmarek@...e.com,
will.deacon@....com, peterz@...radead.org, boqun.feng@...il.com,
mingo@...hat.com, daniel.lezcano@...aro.org, tglx@...utronix.de,
jason@...edaemon.net, marc.zyngier@....com,
gregkh@...uxfoundation.org, jslaby@...e.com, davem@...emloft.net,
mchehab@...nel.org, sfr@...b.auug.org.au, fweisbec@...il.com,
viro@...iv.linux.org.uk, mcgrof@...nel.org, dledford@...hat.com,
bart.vanassche@...disk.com, sstabellini@...nel.org,
daniel.vetter@...ll.ch, mpe@...erman.id.au, msalter@...hat.com,
nicolas.dichtel@...nd.com, james.hogan@...tec.com,
paul.gortmaker@...driver.com, linux@...ck-us.net,
heiko.carstens@...ibm.com, schwidefsky@...ibm.com,
linux-kernel@...r.kernel.org, patches@...ups.riscv.org,
akpm@...ux-foundation.org
Cc: albert@...ive.com, Palmer Dabbelt <palmer@...belt.com>
Subject: [PATCH 05/17] clocksource: New RISC-V SBI timer driver
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems. The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.
This driver attempts to split out the RISC-V ISA specific mechanisms of
accessing the hardware from the clocksource driver by taking a pair of
function pointers to issue the actual RISC-V specific instructions.
Signed-off-by: Palmer Dabbelt <palmer@...belt.com>
---
drivers/clocksource/Kconfig | 8 +++++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/riscv_timer.c | 64 +++++++++++++++++++++++++++++++++++++++
include/linux/timer_riscv.h | 41 +++++++++++++++++++++++++
4 files changed, 114 insertions(+)
create mode 100644 drivers/clocksource/riscv_timer.c
create mode 100644 include/linux/timer_riscv.h
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index fcae5ca6ac92..a5829c0b3ae4 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -607,4 +607,12 @@ config CLKSRC_ST_LPC
Enable this option to use the Low Power controller timer
as clocksource.
+config RISCV_TIMER
+ bool "Timer for the RISC-V platform" if COMPILE_TEST
+ depends on RISCV
+ help
+ This enables the per-hart timer built into all RISC-V systems, which
+ is accessed via both the SBI and the rdcycle instruction. This is
+ required for all RISC-V systems.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 6df949402dfc..20d75b3f22e4 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -73,3 +73,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
obj-$(CONFIG_H8300_TPU) += h8300_tpu.o
obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
new file mode 100644
index 000000000000..6063c7abe21c
--- /dev/null
+++ b/drivers/clocksource/riscv_timer.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/delay.h>
+#include <linux/timer_riscv.h>
+
+/*
+ * See <linux/timer_riscv.h> for the rationale behind pre-allocating per-cpu
+ * timers on RISC-V systems.
+ */
+static DEFINE_PER_CPU(struct clocksource, clock_source);
+static DEFINE_PER_CPU(struct clock_event_device, clock_event);
+
+struct clock_event_device *timer_riscv_device(int cpu)
+{
+ return &per_cpu(clock_event, cpu);
+}
+
+struct clocksource *timer_riscv_source(int cpu)
+{
+ return &per_cpu(clock_source, cpu);
+}
+
+void timer_riscv_init(int cpu_id,
+ unsigned long riscv_timebase,
+ unsigned long long (*rdtime)(struct clocksource *),
+ int (*next)(unsigned long, struct clock_event_device*))
+{
+ struct clocksource *cs = &per_cpu(clock_source, cpu_id);
+ struct clock_event_device *ce = &per_cpu(clock_event, cpu_id);
+
+ *cs = (struct clocksource) {
+ .name = "riscv_clocksource",
+ .rating = 300,
+ .read = rdtime,
+ .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ };
+ clocksource_register_hz(cs, riscv_timebase);
+
+ *ce = (struct clock_event_device){
+ .name = "riscv_timer_clockevent",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .rating = 300,
+ .cpumask = cpumask_of(cpu_id),
+ .set_next_event = next,
+ .set_state_oneshot = NULL,
+ .set_state_shutdown = NULL,
+ };
+ clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
+}
diff --git a/include/linux/timer_riscv.h b/include/linux/timer_riscv.h
new file mode 100644
index 000000000000..f2f91fe46979
--- /dev/null
+++ b/include/linux/timer_riscv.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017 SiFive
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_TIMER_RISCV_H
+#define _LINUX_TIMER_RISCV_H
+
+/*
+ * All RISC-V systems have a timer attached to every hart. These timers can be
+ * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup
+ * events. In order to abstract the architecture-specific timer reading and
+ * setting functions away from the clock event insertion code, we provide
+ * function pointers to the clockevent subsystem that perform two basic operations:
+ * rdtime() reads the timer on the current CPU, and next_event(delta) sets the
+ * next timer event to 'delta' cycles in the future. As the timers are
+ * inherently a per-cpu resource, these callbacks perform operations on the
+ * current hart. There is guaranteed to be exactly one timer per hart on all
+ * RISC-V systems.
+ */
+void timer_riscv_init(int cpu_id,
+ unsigned long riscv_timebase,
+ unsigned long long (*rdtime)(struct clocksource *),
+ int (*next_event)(unsigned long, struct clock_event_device *));
+
+/*
+ * Looks up the clocksource or clock_even_device that cooresponds the given
+ * hart.
+ */
+struct clocksource *timer_riscv_source(int cpuid);
+struct clock_event_device *timer_riscv_device(int cpu_id);
+
+#endif
--
2.13.0
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