linux-kernel - Re: [PATCH 02/13] mpt3sas: SGL to PRP Translation for I/Os to NVMe devices

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CA+RiK67fK5MRxm=Cg4Ymy4us2j27N3aXU1AMpOo0iHsiM_-a8g@mail.gmail.com>
Date:   Fri, 14 Jul 2017 18:57:33 +0530
From:   Suganath Prabu Subramani <suganath-prabu.subramani@...adcom.com>
To:     Keith Busch <keith.busch@...el.com>
Cc:     "JBottomley@...allels.com" <JBottomley@...allels.com>,
        "jejb@...nel.org" <jejb@...nel.org>,
        "hch@...radead.org" <hch@...radead.org>,
        "martin.petersen@...cle.com" <martin.petersen@...cle.com>,
        "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
        "Sathya.Prakash@...adcom.com" <Sathya.Prakash@...adcom.com>,
        "kashyap.desai@...adcom.com" <kashyap.desai@...adcom.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "chaitra.basappa@...adcom.com" <chaitra.basappa@...adcom.com>,
        "sreekanth.reddy@...adcom.com" <sreekanth.reddy@...adcom.com>,
        "linux-nvme@...ts.infradead.org" <linux-nvme@...ts.infradead.org>
Subject: Re: [PATCH 02/13] mpt3sas: SGL to PRP Translation for I/Os to NVMe devices

Hi Keith,
We have made change and submitted V2 of patch set.

Thanks,
Suganath Prabu S

On Wed, Jul 12, 2017 at 5:34 AM, Keith Busch <keith.busch@...el.com> wrote:
> On Tue, Jul 11, 2017 at 01:55:02AM -0700, Suganath Prabu S wrote:
>> +/**
>> + * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
>> + * determine if the driver needs to build a native SGL.  If so, that native
>> + * SGL is built in the special contiguous buffers allocated especially for
>> + * PCIe SGL creation.  If the driver will not build a native SGL, return
>> + * TRUE and a normal IEEE SGL will be built.  Currently this routine
>> + * supports NVMe.
>> + * @ioc: per adapter object
>> + * @mpi_request: mf request pointer
>> + * @smid: system request message index
>> + * @scmd: scsi command
>> + * @pcie_device: points to the PCIe device's info
>> + *
>> + * Returns 0 if native SGL was built, 1 if no SGL was built
>> + */
>> +static int
>> +_base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
>> +     Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
>> +     struct _pcie_device *pcie_device)
>> +{
>
> <snip>
>
>> +     /* Return 0, indicating we built a native SGL. */
>> +     return 1;
>> +}
>
> This function doesn't return 0 ever. Not sure why it's here.
>
> Curious about your device, though, if a nvme native SGL can *not* be
> built, does the HBA firmware then buffer it in its local memory before
> sending/receiving to/from the host?
>
> And if a native SGL can be built, does the NVMe target DMA directly
> to/from host memory, giving a performance boost?