linux-kernel - Re: [RFC PATCH 0/2] Introduce interface for default DMA pool

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Date:   Thu, 20 Jul 2017 11:29:26 +0200
From:   Szemző András <sza@....hu>
To:     Vladimir Murzin <vladimir.murzin@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Russell King - ARM Linux <linux@...linux.org.uk>,
        arnd@...db.de, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        akpm@...ux-foundation.org,
        Alexandre Torgue <alexandre.torgue@...com>,
        robin.murphy@....com, kbuild-all@...org,
        benjamin.gaignard@...aro.org, hch@....de,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        vitaly_kuzmichev@...tor.com, george_davis@...tor.com
Subject: Re: [RFC PATCH 0/2] Introduce interface for default DMA pool

> On 2017. Jul 17., at 10:58, Vladimir Murzin <vladimir.murzin@....com> wrote:
> 
> Hi,
> 
> This is follow-up for Christoph complain of overloading the current
> dma coherent infrastructure with the global pool. To address that I
> implemented Robin's idea of the new interface to the global pool and
> wire up it with (only existent user) ARM NOMMU.  Since I have not
> heard from Vitaly and/or George of their use of global pool, I'm
> leaving ARM MMU part to them.
> 
> [1] https://lkml.org/lkml/2017/7/7/370
> 

I’ve tested the patches on Atmel SAMV7 SoC, and it works for me
without any issues, so you can add my Tested-by.

Thanks for the patches!

Booting Linux on physical CPU 0x0
Linux version 4.13.0-rc1 (root@...el) (gcc version 4.9.2 ( 4.9.2-10)) #3 Wed Jul 19 04:48:18 EDT 2017
CPU: ARMv7-M [410fc271] revision 1 (ARMv7M), cr=00000000
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
OF: fdt: Machine model: SAME70-sampione board
...
Reserved memory: created DMA memory pool at 0x73e00000, size 2 MiB
OF: reserved mem: initialized node linux,dma, compatible id shared-dma-pool
Using ARMv7 PMSA Compliant MPU. Region independence: No, Used 4 of 16 regions
...
DMA: default coherent area is set
...