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Message-ID: <20170721220154.GL19878@codeaurora.org>
Date: Fri, 21 Jul 2017 15:01:54 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Yuantian Tang <andy.tang@....com>
Cc: mturquette@...libre.com, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/2] clk: qoriq: add clock configuration for ls1088a soc
On 04/06, Yuantian Tang wrote:
> Clock on ls1088a chip takes primary clocking input from the external
> SYSCLK signal. The SYSCLK input (frequency) is multiplied using
> multiple phase locked loops (PLL) to create a variety of frequencies
> which can then be passed to a variety of internal logic, including
> cores and peripheral IP modules.
>
> Signed-off-by: Tang Yuantian <andy.tang@....com>
> ---
Applied to clk-next
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