linux-kernel - [PATCH 04/14] amdgpu: powerplay: smu7_hwmgr: Assume display

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 24 Jul 2017 15:35:30 +0200
From:   Ricardo Ribalda Delgado <ricardo.ribalda@...il.com>
To:     Alex Deucher <alexander.deucher@....com>,
        Christian König <christian.koenig@....com>,
        David Airlie <airlied@...ux.ie>, Rex Zhu <Rex.Zhu@....com>,
        Tom St Denis <tom.stdenis@....com>,
        Eric Huang <JinHuiEric.Huang@....com>,
        Huang Rui <ray.huang@....com>,
        Dan Carpenter <dan.carpenter@...cle.com>,
        "Edward O'Callaghan" <funfunctor@...klore1984.net>,
        Kees Cook <keescook@...omium.org>,
        "Andrew F. Davis" <afd@...com>,
        Hawking Zhang <Hawking.Zhang@....com>,
        Baoyou Xie <baoyou.xie@...aro.org>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Colin Ian King <colin.king@...onical.com>,
        Nils Wallménius <nils.wallmenius@...il.com>,
        Joe Perches <joe@...ches.com>, amd-gfx@...ts.freedesktop.org,
        dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Cc:     Ricardo Ribalda Delgado <ricardo.ribalda@...il.com>
Subject: [PATCH 04/14] amdgpu: powerplay: smu7_hwmgr: Assume display_config is zero

display_config is never set, so we can assume it is zero.

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@...il.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 1f01020ce3a9..893e6e846284 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2727,9 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 
 	cgs_get_active_displays_info(hwmgr->device, &info);
 
-	minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
-	minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
-
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_StablePState)) {
 		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
@@ -3928,7 +3925,7 @@ smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 
 	num_active_displays = info.display_count;
 
-	if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true)
+	if (num_active_displays > 1)
 		smu7_notify_smc_display_change(hwmgr, false);
 
 	return 0;
@@ -4032,12 +4029,12 @@ smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 	if (data->display_timing.num_existing_displays != info.display_count)
 		is_update_required = true;
 
-	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-		if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr &&
-			(data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
-			hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
-			is_update_required = true;
-	}
+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+			    PHM_PlatformCaps_SclkDeepSleep) &&
+	    data->display_timing.min_clock_in_sr &&
+	    data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)
+		is_update_required = true;
+
 	return is_update_required;
 }
 
-- 
2.13.2