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Message-ID: <1500978856-5981-9-git-send-email-pdeschrijver@nvidia.com>
Date: Tue, 25 Jul 2017 13:34:09 +0300
From: Peter De Schrijver <pdeschrijver@...dia.com>
To: Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
"Stephen Boyd" <sboyd@...eaurora.org>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
<linux-clk@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH 08/14] clk: tegra: change post IDDQ release delay to 5us
Increase delay after PLL IDDQ release to 5us per PLL specifications.
based on work by Alex Frid <afrid@...dia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@...dia.com>
---
drivers/clk/tegra/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1c36b8a..695ccb4 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
val = pll_readl(pll->params->iddq_reg, pll);
val &= ~BIT(pll->params->iddq_bit_idx);
pll_writel(val, pll->params->iddq_reg, pll);
- udelay(2);
+ udelay(5);
}
if (pll->params->reset_reg) {
--
1.9.1
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