linux-kernel - Re: [PATCH v4 0/9] add support for Sama5d2 audio PLLs and enable ClassD

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Date:   Wed, 26 Jul 2017 08:57:32 +0200
From:   Alexandre Belloni <alexandre.belloni@...e-electrons.com>
To:     Nicolas Ferre <nicolas.ferre@...rochip.com>
Cc:     Quentin Schulz <quentin.schulz@...e-electrons.com>,
        mturquette@...libre.com, sboyd@...eaurora.org, robh+dt@...nel.org,
        mark.rutland@....com, lgirdwood@...il.com, broonie@...nel.org,
        linux@...linux.org.uk, boris.brezillon@...e-electrons.com,
        perex@...ex.cz, tiwai@...e.com, cyrille.pitchen@...ev4u.fr,
        thomas.petazzoni@...e-electrons.com, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        alsa-devel@...a-project.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 0/9] add support for Sama5d2 audio PLLs and enable
 ClassD

On 25/07/2017 at 17:44:19 +0200, Nicolas Ferre wrote:
> On 25/07/2017 at 09:37, Quentin Schulz wrote:
> > This patch series adds support for the audio PLLs and enables ClassD that
> > can be found in ATMEL Sama5d2 SoC.
> > 
> > There are two audio PLLs (PMC and PAD) that shares the same parent (FRAC).
> > FRAC can output between 620 and 700MHz and only multiply the rate of its
> > parent. The two audio PLLs then divide the FRAC rate to best match the
> > asked rate.
> > 
> > I basically took an old patch series posted by Nicolas on December, 6th
> > 2016[1][2][3] and the comments Boris did on the first version[4] Nicolas
> > sent on July, 15th 2015.
> > 
> > I also fixed the function used to compute the divisors, removed useless
> > spinlocks and added a range to the audio frac PLL to stay within vendor's
> > supported range. Clocks that are children of gclk (generated-clk) are now
> > able to propagate rate to the audio PLL clocks when needed.
> > 
> > However, there are multiple children clocks that could technically
> > change the rate of audio_pll (via gck). With the rate locking introduced
> > in Jerome Brunet's patch series[5], the first consumer to enable the clock
> > will be the one definitely setting the rate of the clock. Without the rate
> > locking, the last consumer to set the rate will be able to mess with the
> > rate.
> > Since audio IPs are most likely to request the same rate, we enforce
> > that the only clks able to modify gck rate are those of audio IPs.
> > 
> > To remain consistent, we deny other clocks to be children of audio_pll.
> 
> Quentin,
> 
> Thanks for having revived this series. Everything's okay on my side for
> this v4. I think that my tag isn't missing from any patch of this
> series. Now we surely need to define which path it must take...
> 

I'll take the two dts patches now as the bindings have been acked.
Everything else should probably go through the clk tree.


-- 
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com