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Message-ID: <20170726003650.GH2146@codeaurora.org>
Date: Tue, 25 Jul 2017 17:36:50 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Icenowy Zheng <icenowy@...c.io>
Cc: Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Chen-Yu Tsai <wens@...e.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org, linux-pm@...r.kernel.org,
linux-sunxi@...glegroups.com
Subject: Re: [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk
after rate change
On 07/23, Icenowy Zheng wrote:
> From: Chen-Yu Tsai <wens@...e.org>
>
> This patch utilizes the new PLL clk notifier to gate then ungate the
> PLL CPU clock after rate changes. This should prevent any system hangs
> resulting from cpufreq changes to the clk.
>
> Reported-by: Ondrej Jirman <megous@...ous.com>
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>
> Tested-by: Icenowy Zheng <icenowy@...c.io>
> ---
Acked-by: Stephen Boyd <sboyd@...eaurora.org>
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