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Date:   Thu, 27 Jul 2017 14:32:59 -0300
From:   Thiago Jung Bauermann <bauerman@...ux.vnet.ibm.com>
To:     Ram Pai <linuxram@...ibm.com>
Cc:     linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org,
        linux-arch@...r.kernel.org, linux-mm@...ck.org, x86@...nel.org,
        linux-doc@...r.kernel.org, linux-kselftest@...r.kernel.org,
        arnd@...db.de, corbet@....net, mhocko@...nel.org,
        dave.hansen@...el.com, mingo@...hat.com, paulus@...ba.org,
        aneesh.kumar@...ux.vnet.ibm.com, akpm@...ux-foundation.org,
        khandual@...ux.vnet.ibm.com
Subject: Re: [RFC v6 20/62] powerpc: store and restore the pkey state across context switches


Ram Pai <linuxram@...ibm.com> writes:

> Store and restore the AMR, IAMR and UMOR register state of the task
> before scheduling out and after scheduling in, respectively.
>
> Signed-off-by: Ram Pai <linuxram@...ibm.com>

s/UMOR/UAMOR/

> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index 2ad725e..9429361 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -1096,6 +1096,11 @@ static inline void save_sprs(struct thread_struct *t)
>  		t->tar = mfspr(SPRN_TAR);
>  	}
>  #endif
> +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS
> +	t->amr = mfspr(SPRN_AMR);
> +	t->iamr = mfspr(SPRN_IAMR);
> +	t->uamor = mfspr(SPRN_UAMOR);
> +#endif
>  }
>
>  static inline void restore_sprs(struct thread_struct *old_thread,
> @@ -1131,6 +1136,14 @@ static inline void restore_sprs(struct thread_struct *old_thread,
>  			mtspr(SPRN_TAR, new_thread->tar);
>  	}
>  #endif
> +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS
> +	if (old_thread->amr != new_thread->amr)
> +		mtspr(SPRN_AMR, new_thread->amr);
> +	if (old_thread->iamr != new_thread->iamr)
> +		mtspr(SPRN_IAMR, new_thread->iamr);
> +	if (old_thread->uamor != new_thread->uamor)
> +		mtspr(SPRN_UAMOR, new_thread->uamor);
> +#endif
>  }

Shouldn't the saving and restoring of the SPRs be guarded by a check for
whether memory protection keys are enabled? What happens when trying to
access these registers on a CPU which doesn't have them?

-- 
Thiago Jung Bauermann
IBM Linux Technology Center

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