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Message-ID: <1501588965.2792.121.camel@kernel.crashing.org>
Date: Tue, 01 Aug 2017 22:02:45 +1000
From: Benjamin Herrenschmidt <benh@...nel.crashing.org>
To: Will Deacon <will.deacon@....com>,
Peter Zijlstra <peterz@...radead.org>
Cc: torvalds@...ux-foundation.org, oleg@...hat.com,
paulmck@...ux.vnet.ibm.com, mpe@...erman.id.au, npiggin@...il.com,
linux-kernel@...r.kernel.org, mingo@...nel.org,
stern@...land.harvard.edu, Mel Gorman <mgorman@...e.de>,
Rik van Riel <riel@...hat.com>
Subject: Re: [RFC][PATCH 1/5] mm: Rework {set,clear,mm}_tlb_flush_pending()
On Tue, 2017-08-01 at 11:31 +0100, Will Deacon wrote:
> Looks like that's what's currently relied upon:
>
> /* Clearing is done after a TLB flush, which also provides a barrier. */
>
> It also provides barrier semantics on arm/arm64. In reality, I suspect
> all archs have to provide some order between set_pte_at and flush_tlb_range
> which is sufficient to hold up clearing the flag. :/
Hrm... not explicitely.
Most archs (powerpc among them) have set_pte_at be just a dumb store,
so the only barrier it has is the surrounding PTL.
Now flush_tlb_range() I assume has some internal strong barriers but
none of that is well defined or documented at all, so I suspect all
bets are off.
Ben.
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