lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Sun, 6 Aug 2017 10:01:39 +0800 From: Chen-Yu Tsai <wens@...e.org> To: Icenowy Zheng <icenowy@...c.io> Cc: Ulf Hansson <ulf.hansson@...aro.org>, Maxime Ripard <maxime.ripard@...e-electrons.com>, Chen-Yu Tsai <wens@...e.org>, "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, linux-kernel <linux-kernel@...r.kernel.org>, linux-sunxi <linux-sunxi@...glegroups.com> Subject: Re: [linux-sunxi] [PATCH 1/2] mmc: sunxi: fix support for new timings mode only SoCs On Sat, Aug 5, 2017 at 5:35 AM, Icenowy Zheng <icenowy@...c.io> wrote: > The A83T MMC support code introduces the timings mode switch, however > such a switch doesn't exist on new SoCs with only new timings mode. > > Only execute the switch if the SoC really have the timings mode switch, > to fix the regression shown on new timings mode only SoCs (A64, H5, > etc). > > Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use both > old and new timings") You could make it easier to read by aligning the wrapped line with opening parenthesis and double quote. And you don't need the newline here. > > Signed-off-by: Icenowy Zheng <icenowy@...c.io> This must have slipped through when I reworked the mmc quirks. Reviewed-by: Chen-Yu Tsai <wens@...e.org>
Powered by blists - more mailing lists