linux-kernel - Re: [PATCH v2 4/5] PCI: mediatek: Add new generation controller support

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Message-ID: <1502077231.24341.29.camel@mtksdaap41>
Date:   Mon, 7 Aug 2017 11:40:31 +0800
From:   Honghui Zhang <honghui.zhang@...iatek.com>
To:     Ryder Lee <ryder.lee@...iatek.com>
CC:     Bjorn Helgaas <helgaas@...nel.org>, <bhelgaas@...gle.com>,
        <robh@...enl.org>, <robh+dt@...nel.org>, <matthias.bgg@...il.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>, <linux-pci@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <yingjoe.chen@...iatek.com>, <eddie.huang@...iatek.com>,
        <hongkun.cao@...iatek.com>, <youlin.pei@...iatek.com>,
        <yong.wu@...iatek.com>, <yt.shen@...iatek.com>,
        <sean.wang@...iatek.com>, <xinping.qian@...iatek.com>
Subject: Re: [PATCH v2 4/5] PCI: mediatek: Add new generation controller
 support

On Sat, 2017-08-05 at 14:16 +0800, Ryder Lee wrote:
> On Sat, 2017-08-05 at 12:52 +0800, Ryder Lee wrote:
> > Hi Honghui, Bjorn,
> > 
> > On Fri, 2017-08-04 at 08:18 -0500, Bjorn Helgaas wrote:
> > > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote:
> > > > On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote:
> > > > > > +
> > > > > > +static struct mtk_pcie_port *mtk_pcie_find_port(struct mtk_pcie *pcie,
> > > > > > +						struct pci_bus *bus, int devfn)
> > > > > > +{
> > > > > > +	struct pci_dev *dev;
> > > > > > +	struct pci_bus *pbus;
> > > > > > +	struct mtk_pcie_port *port, *tmp;
> > > > > > +
> > > > > > +	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
> > > > > > +		if (bus->number == 0 && port->index == PCI_SLOT(devfn)) {
> > > > > > +			return port;
> > > > > > +		} else if (bus->number != 0) {
> > > > > > +			pbus = bus;
> > > > > > +			do {
> > > > > > +				dev = pbus->self;
> > > > > > +				if (port->index == PCI_SLOT(dev->devfn))
> > > > > > +					return port;
> > > > > > +				pbus = dev->bus;
> > > > > > +			} while (dev->bus->number != 0);
> > > > > > +		}
> > > > > > +	}
> > > > > > +
> > > > > > +	return NULL;
> > > > > 
> > > > > You should be able to use sysdata to avoid searching the list.
> > > > > See drivers/pci/host/pci-aardvark.c, for example.
> > > > > 
> > > > 
> > > > I could put the mtk_pcie * in sysdata, but still need to searching the
> > > > list to get the mtk_pcie_port *, how about:
> > > > 
> > > > 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
> > > > 		if (port->index == PCI_SLOT(devfn))
> > > > 			return port;
> > > > 	}
> > > 
> > > No.  Other drivers don't need to search the list.  Please take a look
> > > at them and see how they solve this problem.  I don't think your
> > > hardware is fundamentally different in a way that means you need to
> > > search when the others don't.
> > > 
> > 
> > I'm not directly involved in this generation, but I guess the main reason why Honghui need to do that is just because this hardware access configuration space via per-port registers, not just for the guard.  
> > Currently, We had a host bridge with two ports (two subnodes in binding text), thus he tried to tells them apart so that he can get the correct registers.
> > 
> > Some platforms don't need to do that since they just have a single port (no more subnodes), the others might have specific/shared registers to access configuration space. (e.g. Tegra, MTK legacy IP block).
> > Or, he can split them into two independent nodes, but it will break common probing flow by doing so. (I'd prefer to use subnodes.)
> > 
> > Ryder
> > 
> 
> Sorry for the typesetting in previous mail and noise again,
> 
> I've took a look at pci-rcar-gen2.c, this is a similar case I can found
> for Honghui's case. It gathers two ports reg regions into one, and uses
> the "slot id" to calculate the cfg base of each port.
> 
> Perhaps this is a example for those who need to use subnodes and use
> port registers for cfg operation. Not sure whether it's worthwhile doing
> that since we need to changes ports/host structures.
> 
> Ryder.
> 
As Ryder's description, Mediatek's new generation HW blocks has two
separate ports, they have separate control register base address. We
must touch the per-port control register to access the EP's
configuration space. One port's control register is the only way to
access the EP's configuration space(the EP which is connect under this
very port).
Given an EP device, we need to determine which ports it's been
connected, and get the base address for that port. It's a bit like
pci-tegra/pci-mvebu.

Seems list is not forbidden, pci-tegra search the list to identify the
ports[1], mvebu use point array to search the ports[2], they have the
same functionality through different approach. I may propose another
patch to make the code like mvebu[2] if you insist, but I'm prefer the
current list way.

[1]http://elixir.free-electrons.com/linux/v4.13-rc4/source/drivers/pci/host/pci-tegra.c#L456
[2]http://elixir.free-electrons.com/linux/v4.13-rc4/source/drivers/pci/host/pci-mvebu.c#L780

thanks.
>