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Message-ID: <20580261.Hd2GIELq42@phil>
Date:   Tue, 08 Aug 2017 00:52:46 +0200
From:   Heiko Stuebner <heiko@...ech.de>
To:     Andy Yan <andy.yan@...k-chips.com>
Cc:     robh+dt@...nel.org, shawn.lin@...k-chips.com,
        zhangqing@...k-chips.com, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, mturquette@...libre.com,
        sboyd@...eaurora.org, linux-rockchip@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 05/23] clk: rockchip: fix up the pll clks error for rv1108 SoC

Am Mittwoch, 2. August 2017, 16:33:04 CEST schrieb Andy Yan:
> From: Elaine Zhang <zhangqing@...k-chips.com>
> 
> fix up the lock_shift describe error.
> remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll.
> 
> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
> Signed-off-by: Andy Yan <andy.yan@...k-chips.com>

applied for 4.14


Thanks
Heiko

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