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Date: Tue, 08 Aug 2017 17:11:51 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: Elaine Zhang <zhangqing@...k-chips.com>
Cc: mturquette@...libre.com, sboyd@...eaurora.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
robh+dt@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, xxx@...k-chips.com, xf@...k-chips.com,
huangtao@...k-chips.com, shawn.lin@...k-chips.com,
andy.yan@...k-chips.com
Subject: Re: [PATCH v3 5/9] clk: rockchip: fix up the pll clks error for rv1108 SoC
Am Dienstag, 8. August 2017, 15:17:55 CEST schrieb Elaine Zhang:
> fix up the lock_shift describe error.
> remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll.
>
> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
already picked the one from Andy's v2, so ignored this one
Heiko
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