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Message-ID: <6a652887-5075-d406-2b9e-ebb77edeeb31@codeaurora.org>
Date: Wed, 9 Aug 2017 14:50:27 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Bjorn Andersson <bjorn.andersson@...aro.org>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-soc@...r.kernel.org
Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: Specify dload address for
msm8916 and msm8996
On 08/09/2017 01:10 PM, Bjorn Andersson wrote:
> On msm8916 and msm8996 boards a secure io-write is used to write the
> magic for selecting "download mode", specify this address in the
> DeviceTree.
>
> Note that qcom_scm.download_mode=1 must be specified on the kernel
> command line for the kernel to attempt selecting download mode.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 039991f80831..b7197f2e7209 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -241,6 +241,8 @@
> clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
> clock-names = "core", "bus", "iface";
> #reset-cells = <1>;
> +
> + qcom,dload-mode = <&tcsr>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 8f085716e258..2eee6a33f22b 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -261,6 +261,8 @@
> firmware {
> scm {
> compatible = "qcom,scm-msm8996";
> +
> + qcom,dload-mode = <&tcsr>;
We don't need an offset into tcsr?
> };
> };
>
> @@ -287,6 +289,11 @@
> reg = <0x740000 0x20000>;
> };
>
> + tcsr: syscon@...7000 {
This doesn't match reg property.
> + compatible = "qcom,tcsr-msm8996", "syscon";
> + reg = <0x7a0000 0x18000>;
> + };
> +
> intc: interrupt-controller@...0000 {
> compatible = "arm,gic-v3";
> #interrupt-cells = <3>;
--
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