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Message-ID: <20170809180007.GA9100@otc-nc-03>
Date: Wed, 9 Aug 2017 11:00:08 -0700
From: "Raj, Ashok" <ashok.raj@...el.com>
To: Casey Leedom <leedom@...lsio.com>
Cc: Bjorn Helgaas <helgaas@...nel.org>,
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Subject: Re: [PATCH v9 1/4] PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
On Wed, Aug 09, 2017 at 04:46:07PM +0000, Casey Leedom wrote:
> | From: Raj, Ashok <ashok.raj@...el.com>
> | Sent: Wednesday, August 9, 2017 8:58 AM
> | ...
> | As Casey pointed out in an earlier thread, we choose the heavy hammer
> | approach because there are some that can lead to data-corruption as opposed
> | to perf degradation.
>
> Careful. As far as I'm aware, there is no Data Corruption problem
> whatsoever with Intel Root Ports and processing of Transaction Layer Packets
> with and without the Relaxed Ordering Attribute set.
That's right.. no data-corruption on Intel parts :-).. It was with
other vendor. Only performance issue with intel root-ports in the parts
identified by the optimization guide.
Cheers,
AShok
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