linux-kernel - [tip:perf/core] perf/x86/amd/uncore: Get correct number of cores sharing last level cache

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Date:   Thu, 10 Aug 2017 05:02:57 -0700
From:   tip-bot for Janakarajan Natarajan <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, hpa@...or.com, suravee.suthikulpanit@....com,
        Janakarajan.Natarajan@....com, alexander.shishkin@...ux.intel.com,
        torvalds@...ux-foundation.org, mingo@...nel.org, acme@...nel.org,
        bp@...e.de, linux-kernel@...r.kernel.org, peterz@...radead.org
Subject: [tip:perf/core] perf/x86/amd/uncore: Get correct number of cores
 sharing last level cache

Commit-ID:  ab027620e95987b5f0145013090a109b4152d23b
Gitweb:     http://git.kernel.org/tip/ab027620e95987b5f0145013090a109b4152d23b
Author:     Janakarajan Natarajan <Janakarajan.Natarajan@....com>
AuthorDate: Wed, 14 Jun 2017 11:26:58 -0500
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 10 Aug 2017 12:08:39 +0200

perf/x86/amd/uncore: Get correct number of cores sharing last level cache

In Family 17h, the number of cores sharing a cache level is obtained
from the Cache Properties CPUID leaf (0x8000001d) by passing in the
cache level in ECX. In prior families, a cache level of 2 was used to
determine this information.

To get the right information, irrespective of Family, iterate over
the cache levels using CPUID 0x8000001d. The last level cache is the
last value to return a non-zero value in EAX.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@....com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Reviewed-by: Borislav Petkov <bp@...e.de>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: http://lkml.kernel.org/r/5ab569025b39cdfaeca55b571d78c0fc800bdb69.1497452002.git.Janakarajan.Natarajan@amd.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/amd/uncore.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index e34f8a6..f5cbbba 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -400,11 +400,24 @@ static int amd_uncore_cpu_starting(unsigned int cpu)
 
 	if (amd_uncore_llc) {
 		unsigned int apicid = cpu_data(cpu).apicid;
-		unsigned int nshared;
+		unsigned int nshared, subleaf, prev_eax = 0;
 
 		uncore = *per_cpu_ptr(amd_uncore_llc, cpu);
-		cpuid_count(0x8000001d, 2, &eax, &ebx, &ecx, &edx);
-		nshared = ((eax >> 14) & 0xfff) + 1;
+		/*
+		 * Iterate over Cache Topology Definition leaves until no
+		 * more cache descriptions are available.
+		 */
+		for (subleaf = 0; subleaf < 5; subleaf++) {
+			cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx);
+
+			/* EAX[0:4] gives type of cache */
+			if (!(eax & 0x1f))
+				break;
+
+			prev_eax = eax;
+		}
+		nshared = ((prev_eax >> 14) & 0xfff) + 1;
+
 		uncore->id = apicid - (apicid % nshared);
 
 		uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);