linux-kernel - Re: perf: multiple mmap of fd behavior on x86/ARM

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 14 Aug 2017 11:57:29 +0100
From:   Will Deacon <will.deacon@....com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     Mark Rutland <mark.rutland@....com>,
        Vince Weaver <vincent.weaver@...ne.edu>,
        linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...hat.com>,
        Paul Turner <pjt@...gle.com>,
        Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
Subject: Re: perf: multiple mmap of fd behavior on x86/ARM

On Fri, Aug 11, 2017 at 04:53:30PM +0200, Peter Zijlstra wrote:
> On Fri, Aug 11, 2017 at 12:06:39PM +0100, Mark Rutland wrote:
> > On Fri, Aug 11, 2017 at 12:52:52PM +0200, Peter Zijlstra wrote:
> > > On Fri, Aug 11, 2017 at 11:01:27AM +0100, Mark Rutland wrote:
> > > > On Thu, Aug 10, 2017 at 02:48:52PM -0400, Vince Weaver wrote:
> > > > > 
> > > > > So I was working on my perf_event_tests on ARM/ARM64 (the end goal was to 
> > > > > get ARM64 rdpmc support working, but apparently those patches never made 
> > > > > it upstream?)
> > > > 
> > > > IIUC by 'rdpmc' you mean direct userspace counter access?
> > > > 
> > > > Patches for that never made it upstream. Last I saw, there were no
> > > > patches in a suitable state for review.
> > > > 
> > > > There are also difficulties (e.g. big.LITTLE systems where the number of
> > > > counters can differ across CPUs) which have yet to be solved.
> > > 
> > > How would that be a problem? The API gives an explicit index to use with
> > > the 'rdpmc' instruction.
> > 
> > It's a problem because access to unimplemented counters trap. So if a
> > task gets migrated from a CPU with N counters to one with N-1, accessing
> > counter N would be problematic.
> > 
> > So we'd need to account for that somehow, in addition to the usual
> > sequence counter fun to verify the index was valid when the access was
> > performed.
> 
> Aah, you need restartable-sequences :-)

Or, in the absence of those, I wouldn't mind only supporting this for
non-big/little platforms initially.

Will