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Date:   Mon, 14 Aug 2017 14:21:05 +0800
From:   Chen-Yu Tsai <wens@...e.org>
To:     Icenowy Zheng <icenowy@...c.io>
Cc:     Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Chen-Yu Tsai <wens@...e.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        devicetree <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [linux-sunxi] [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng <icenowy@...c.io> wrote:
> The pin controller of H5 has three IRQs at the chip's GIC, which
> represents three banks of pinctrl IRQs. However, the device tree used to
> miss the third IRQ of the pin controller, which makes the PG bank IRQ
> not usable.
>
> Add the missing IRQ to the pinctrl node.
>
> Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi")
> Signed-off-by: Icenowy Zheng <icenowy@...c.io>

Applied as fixes for 4.13.

ChenYu

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