linux-kernel - Re: [PATCH 2/2] PCI: dwc: spear13xx: utilize dw_pcie_readX_dbi/dw_pcie_writeX

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Message-ID: <20170814180912.GB32525@bhelgaas-glaptop.roam.corp.google.com>
Date:   Mon, 14 Aug 2017 13:09:12 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Niklas Cassel <niklas.cassel@...s.com>
Cc:     Pratyush Anand <pratyush.anand@...il.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Niklas Cassel <niklass@...s.com>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] PCI: dwc: spear13xx: utilize
 dw_pcie_readX_dbi/dw_pcie_writeX_dbi macros

On Fri, Jul 14, 2017 at 02:07:35PM +0200, Niklas Cassel wrote:
> Signed-off-by: Niklas Cassel <niklas.cassel@...s.com>

Pratyush, are you OK with this?

> ---
>  drivers/pci/dwc/pcie-spear13xx.c | 22 ++++++++++------------
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pcie-spear13xx.c b/drivers/pci/dwc/pcie-spear13xx.c
> index 80897291e0fb..7ebfbf6086fe 100644
> --- a/drivers/pci/dwc/pcie-spear13xx.c
> +++ b/drivers/pci/dwc/pcie-spear13xx.c
> @@ -92,34 +92,32 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
>  	 * default value in capability register is 512 bytes. So force
>  	 * it to 128 here.
>  	 */
> -	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
> +	val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL);
>  	val &= ~PCI_EXP_DEVCTL_READRQ;
> -	dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
> +	dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val);
>  
> -	dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
> -	dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
> +	dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A);
> +	dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80);
>  
>  	/*
>  	 * if is_gen1 is set then handle it, so that some buggy card
>  	 * also works
>  	 */
>  	if (spear13xx_pcie->is_gen1) {
> -		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
> -			     4, &val);
> +		val = dw_pcie_readl_dbi(pci, exp_cap_off + PCI_EXP_LNKCAP);
>  		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
>  			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
>  			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> -			dw_pcie_write(pci->dbi_base + exp_cap_off +
> -				      PCI_EXP_LNKCAP, 4, val);
> +			dw_pcie_writel_dbi(pci, exp_cap_off + PCI_EXP_LNKCAP,
> +					   val);
>  		}
>  
> -		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
> -			     2, &val);
> +		val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_LNKCTL2);
>  		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
>  			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
>  			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
> -			dw_pcie_write(pci->dbi_base + exp_cap_off +
> -				      PCI_EXP_LNKCTL2, 2, val);
> +			dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_LNKCTL2,
> +					   val);
>  		}
>  	}
>  
> -- 
> 2.11.0
>