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Message-ID: <1502779370-30150-10-git-send-email-weiyi.lu@mediatek.com>
Date: Tue, 15 Aug 2017 14:42:50 +0800
From: <weiyi.lu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...eaurora.org>
CC: James Liao <jamesjj.liao@...iatek.com>,
Fan Chen <fan.chen@...iatek.com>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<srv_heupstream@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [PATCH v1 9/9] arm: dts: Add power controller device node of MT2712
From: Weiyi Lu <weiyi.lu@...iatek.com>
add power controller node for MT2712
Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 6338a1f..3fc2eee 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -165,6 +165,21 @@
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
};
+ scpsys: scpsys@...06000 {
+ compatible = "mediatek,mt2712-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_JPGDEC_SEL>,
+ <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>;
+ clock-names = "mm", "mfg", "venc",
+ "jpgdec", "audio", "vdec";
+ infracfg = <&infracfg>;
+ };
+
uart5: serial@...0f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
--
1.9.1
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