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Date:   Thu, 17 Aug 2017 10:56:35 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Alex Williamson' <alex.williamson@...hat.com>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>
CC:     Jike Song <jike.song@...el.com>, Neo Jia <cjia@...dia.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        Eric Auger <eric.auger@...hat.com>,
        Alexey Kardashevskiy <aik@...abs.ru>,
        Robin Murphy <robin.murphy@....com>,
        Joerg Roedel <joro@...tes.org>,
        Kyle Mahlkuch <Kyle.Mahlkuch@....com>,
        Vlad Tsyrklevich <vlad@...rklevich.net>,
        "kvm-ppc@...r.kernel.org" <kvm-ppc@...r.kernel.org>,
        "iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
        Yongji Xie <elohimes@...il.com>,
        Kirti Wankhede <kwankhede@...dia.com>,
        Mauricio Faria de Oliveira <mauricfo@...ux.vnet.ibm.com>,
        Paul Mackerras <paulus@...ba.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Arvind Yadav <arvind.yadav.cs@...il.com>,
        "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
        David Woodhouse <dwmw2@...radead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        David Gibson <david@...son.dropbear.id.au>
Subject: RE: [RFC PATCH v5 0/5] vfio-pci: Add support for mmapping MSI-X
 table

From: Alex Williamson
> Sent: 16 August 2017 17:56
...
> Firmware pissing match...  Processors running with 8k or less page size
> fall within the recommendations of the PCI spec for register alignment
> of MMIO regions of the device and this whole problem becomes less of an
> issue.

Actually if qemu is causing the MSI-X table accesses to fault, why doesn't
it just lie to the guest about the physical address of the MSI-X table?
Then mmio access to anything in the same physical page will just work.

It has already been pointed out that you can't actually police the
interrupts that are raised without host hardware support.

Actually, putting other vectors in the MSI-X table is boring, most
drivers will ignore unexpected interrupts.
Much more interesting are physical memory addresses and accessible IO
addresses.
Of course, a lot of boards have PCI master capability and can probably
be persuaded to do writes to specific location anyway.

	David

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