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Message-ID: <55cc4f69-95a4-65e9-234d-880bfcf1fed0@cogentembedded.com>
Date: Fri, 18 Aug 2017 12:58:30 +0300
From: Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To: Stephan Gatzka <stephan.gatzka@...il.com>, peppe.cavallaro@...com,
alexandre.torgue@...com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] net: stmmac: socfgpa: Ensure emac bit set in sys manager
for MII/GMII/SGMII.
Hello!
On 8/18/2017 9:55 AM, Stephan Gatzka wrote:
> When using MII/GMII/SGMII in the Altera SoC, the phy needs to be
> wired through the FPGA. To ensure correct behavior, the appropriate
> bit in the System Manager FPGA Interface Group register needs to be
> set.
>
> Signed-off-by: Stephan Gatzka <stephan.gatzka@...il.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> index 17d4bba..d7c231b 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> @@ -269,7 +269,10 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
> ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
> ctrl |= val << reg_shift;
>
> - if (dwmac->f2h_ptp_ref_clk) {
> + if ((dwmac->f2h_ptp_ref_clk) ||
> + (phymode == PHY_INTERFACE_MODE_MII) ||
> + (phymode == PHY_INTERFACE_MODE_GMII) ||
> + (phymode == PHY_INTERFACE_MODE_SGMII)) {
Inner parens not needed at all (especially the first pair).
[...]
MBR, Sergei
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