linux-kernel - [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT

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Message-ID: <lsq.1503062000.223402560@decadent.org.uk>
Date:   Fri, 18 Aug 2017 14:13:20 +0100
From:   Ben Hutchings <ben@...adent.org.uk>
To:     linux-kernel@...r.kernel.org, stable@...r.kernel.org
CC:     akpm@...ux-foundation.org, "Fuxin Zhang" <zhangfx@...ote.com>,
        "Huacai Chen" <chenhc@...ote.com>,
        "Steven J . Hill" <Steven.Hill@...iumnetworks.com>,
        "Ralf Baechle" <ralf@...ux-mips.org>,
        "Zhangjin Wu" <wuzhangjin@...il.com>, linux-mips@...ux-mips.org,
        "John Crispin" <john@...ozen.org>
Subject: [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

3.16.47-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: Huacai Chen <chenhc@...ote.com>

commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.

Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.

Signed-off-by: Huacai Chen <chenhc@...ote.com>
Cc: John Crispin <john@...ozen.org>
Cc: Steven J . Hill <Steven.Hill@...iumnetworks.com>
Cc: Fuxin Zhang <zhangfx@...ote.com>
Cc: Zhangjin Wu <wuzhangjin@...il.com>
Cc: linux-mips@...ux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@...ux-mips.org>
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings <ben@...adent.org.uk>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1193,6 +1193,7 @@ config CPU_LOONGSON3
 	select CPU_SUPPORTS_HUGEPAGES
 	select WEAK_ORDERING
 	select WEAK_REORDERING_BEYOND_LLSC
+	select MIPS_L1_CACHE_SHIFT_6
 	help
 		The Loongson 3 processor implements the MIPS64R2 instruction
 		set with many extensions.