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Message-ID: <23515351.KtMKrjq6Hm@phil>
Date:   Fri, 25 Aug 2017 11:23:17 +0200
From:   Heiko Stuebner <heiko@...ech.de>
To:     David Wu <david.wu@...k-chips.com>
Cc:     linus.walleij@...aro.org, huangtao@...k-chips.com,
        andy.yan@...k-chips.com, linux-rockchip@...ts.infradead.org,
        linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] pinctrl: rockchip: Add rv1108 recalculated iomux support

Am Mittwoch, 23. August 2017, 16:00:07 CEST schrieb David Wu:
> The pins from GPIO1A0 to GPIO1B1 are special, need to recalculate
> iomux. And the register offset is larger than the u8 range, so changed
> to u32.
> 
> Signed-off-by: David Wu <david.wu@...k-chips.com>

While I'm still struggling trying to understand why some chip-designer
would move these iomux settings into the general SOC_CON registers,
this matches the documentation for the rv1108, so

Reviewed-by: Heiko Stuebner <heiko@...ech.de>


Heiko

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