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Date:   Mon, 28 Aug 2017 10:05:33 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Koji Matsuoka <koji.matsuoka.xm@...esas.com>,
        Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
        Thong Ho <thong.ho.px@....renesas.com>,
        Nhan Nguyen <nhan.nguyen.yb@...esas.com>
Subject: [PATCH 4.4 28/53] drm: rcar-du: Fix display timing controller parameter

4.4-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Koji Matsuoka <koji.matsuoka.xm@...esas.com>

commit 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 upstream.

There is a bug in the setting of the DES (Display Enable Signal)
register. This current setting occurs 1 dot left shift. The DES
register should be set minus one value about the specifying value
with H/W specification. This patch corrects it.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@...esas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>
Signed-off-by: Thong Ho <thong.ho.px@....renesas.com>
Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@...esas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -171,7 +171,7 @@ static void rcar_du_crtc_set_display_tim
 					mode->crtc_vsync_start - 1);
 	rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 
-	rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
+	rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
 	rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 }
 


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