lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 30 Aug 2017 05:01:09 +0200
From:   Philipp Rossak <embed3d@...il.com>
To:     robh+dt@...nel.org, mark.rutland@....com, linux@...linux.org.uk,
        maxime.ripard@...e-electrons.com, wens@...e.org
Cc:     Philipp Rossak <embed3d@...il.com>, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH 6/7] ARM: dts: sun8i: h3: Adding UART3 RTS and CTS Pins

From: Philipp Rossak <embed3d@...il.com>

This node adds the definition for the UART3 RTS and CTS Pins

That makes it able to use UART3 with RTS and CTS.

Signed-off-by: Philipp Rossak <embed3d@...il.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d38282b..7f750ef 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -381,6 +381,11 @@
 				pins = "PA13", "PA14";
 				function = "uart3";
 			};
+
+			uart3_rts_cts_pins: uart3_rts_cts {
+				pins = "PA15", "PA16";
+				function = "uart3";
+			};
 		};
 
 		timer@...20c00 {
-- 
2.7.4

Powered by blists - more mailing lists