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Message-ID: <20170901225514.GE21656@codeaurora.org>
Date: Fri, 1 Sep 2017 15:55:14 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Quentin Schulz <quentin.schulz@...e-electrons.com>
Cc: mturquette@...libre.com, robh+dt@...nel.org, mark.rutland@....com,
lgirdwood@...il.com, broonie@...nel.org,
nicolas.ferre@...rochip.com, alexandre.belloni@...e-electrons.com,
linux@...linux.org.uk, boris.brezillon@...e-electrons.com,
perex@...ex.cz, tiwai@...e.com, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
alsa-devel@...a-project.org, linux-arm-kernel@...ts.infradead.org,
cyrille.pitchen@...ev4u.fr, thomas.petazzoni@...e-electrons.com,
Nicolas Ferre <nicolas.ferre@...el.com>
Subject: Re: [PATCH v5 3/7] clk: at91: add audio pll clock drivers
On 08/10, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
>
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers. Each of them could modify the
> rate of the main audio pll parent.
>
> The main audio pll clock can output 620MHz to 700MHz.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@...el.com>
> Signed-off-by: Quentin Schulz <quentin.schulz@...e-electrons.com>
> Acked-by: Boris Brezillon <boris.brezillon@...e-electrons.com>
> ---
Applied to clk-next
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